This invention relates generally to manufacturing processes requiring lithography, and more particularly to an X/Y vernier for ascertaining misalignment of a lithographic step relative to an underlying pattern.
Lithography has a broad range of industrial applications, including the manufacture of integrated circuits, flat-panel displays, and micromachines.
The lithographic process transfers a mask, or reticle, pattern onto a substrate. Usually, the pattern is formed in a photoresist layer overlying the substrate. The pattern may then be etched into a material underlying the photoresist layer. For example, in the case of inlaid copper, copper is deposited into trenches formed by the etch step and then polished using CMP to form the desired copper lines. This layer will include a reference pattern. A second device layer to be formed will be patterned using photoresist. The second layer will include an active pattern in addition to the desired device related features. Prior to completion of the process associated with the second device layer, the photoresist pattern is compared to the underlying reference pattern to confirm alignment, or measure misalignment.
Referring now to FIG. 1 (prior art), a typical vernier 10 is shown. The vernier is comprised of two patterns aligned adjacent to each other. The first pattern 12, which is also called the reference pattern, is assimilated into the substrate, or an overlying layer, depositing material, by etching, or otherwise delineating the pattern. The second pattern 14, which is also called the active pattern, is a layer of photoresist that has been patterned. This vernier could be used, for example, to check the alignment during the formation of multiple metal layers. It is necessary to check the alignment of the second pattern 14 relative to the first pattern 12 prior to continuing with the subsequent process steps. If the alignment is beyond a predetermined tolerance, the second pattern 14 can be removed and redone, prior to additional processing. The alignment may be checked by viewing the pattern under a microscope.
A proper alignment would be shown by proper alignment of the first centerline 16, and the second centerline 18. As shown in FIG. 1 (prior art) the patterns are out of alignment as the two most apparently aligned features are reference pattern mark 20 and active pattern mark 22. If this misalignment were outside of an acceptable range, the second pattern would have to be removed, re-exposed, and re-checked. If the wafer is not reworked while out of alignment there a significant likelihood of producing a wafer with poor yield.
A disadvantage of this type of vernier is that only one direction is available for inspection at a time. As shown in FIG. 1 (prior art) only the x-direction can be determined. A second vernier, rotated 90-degrees relative to the one shown, will need to be provided in order to inspect alignment along the y-direction. Although these verniers are usually formed within a scribe sheet, in order to avoid interference with device structures, they may not be easy to find. The x-direction and the y-direction may be a relatively large distance from each other. Even if the x-direction and y-direction are in close proximity, it will require reading two verniers to determine proper alignment in both axes. This wastes time during inspections, and may slow wafer fab processing. In some cases where the vernier is not within a scribe line, it may also waste valuable wafer area that could be used for constructing devices.